|09 May||Monday||09:00 – 12:00 & 14:00 – 17:00 CEST/GMT+2||6 Hours|
|10 May||Tuesday||09:00 – 12:00 & 14:00 – 17:00 CEST/GMT+2||6 Hours|
|11 May||Wednesday||09:00 – 12:00 & 14:00 – 17:00 CEST/GMT+2||6 Hours|
|12 May||Thursday||09:00 – 12:00 & 14:00 – 17:00 CEST/GMT+2||6 Hours|
Students will complete the class with a full understanding of the RISC-V architecture and its variants, how to identify/analyze a RISC-V processor, and how to target and exploit an application or kernel running on a RISC-V CPU. Students will learn how the architecture’s formal definition differs from implementations of the processor specification, and will learn how to target subtleties in the specification that grant implementors the flexibility to introduce potential architecture flaws that can be exploited in order to cross privilege boundaries or leak/exfil privileged data.
Variations of RISC-V technology will be discussed, such as the “unhackable” Morpheus microarchitecture, production variants such as SiFive’s product line, and security focused chips such as HexFive and LowRISC.
Don A. Bailey is a well known cyber security professional that has been on the bleeding edge of security research for 20 years. In his storied career, he has been lucky enough to have several key industry firsts: the first car hack, the first global cellular hack, the first GPS hack, the largest compression algorithm hack, the first Apple hardware IoT security model hack, and the first RISC-V 0day. Regarding RISC-V security, Don got in early to the architecture, joining the RISC-V organization in 2016. Don’s research uncovered the first privilege model exploit, which he demonstrated at HITB 2017. Don currently works to integrate security into RISC-V as the chair of the Security Response Team, which is releasing strategies for RISC-V security in 2022. Mr Bailey resides in Michigan with his son, Pierce, and his dog Arthur.